D3T 2008 - Call for Participation

Registration Deadline September 29th, 2008!

CALL FOR PARTICIPATION

Scope -- Key Dates -- Registration -- Advance Program -- Committees

Scope

Technology scaling is introducing yield as main issue to design and test engineers. Various types of defects are presenting unique challenges to the yield enhancement community. New test data based methodologies are required to detect, monitor, and comprehend the various defect mechanisms at sub-50nm technology nodes and their impact on yield. Data-driven testing (DDT) has been in practice for a number of years and often used for yield learning and analysis. It is now gaining attention more than ever in adaptive test. DDT uses data to reduce defect levels, increase reliability, and to diagnose and solve yield problems. DDT can provide feedbacks on which tests to add/remove, or test subsets (e.g. reduced MINVDD test sets). It can also be utilized for improving quality of logic test patterns (e.g. small delay defect, defect-based) vs. outlier analysis tests (e.g. MINVDD, IDDQ). However, test data has not been easily accessible by smaller companies and researchers in academia. These issues will be discussed in this year’s D3T workshop.

Key Dates

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Advance Registration Deadline: September 29, 2008!

Registration

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Registration: https://www.badgeguys.com/reg/2008/itc/register.aspx

Advance Registration Deadline: Sep. 29, 2008!

Advance Program

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Thursday -- Friday

October 30, 2008 (Thursday)

4:00 PM - 5:00 PM	OPENING SESSION
	Opening Remarks M. Tehranipoor (Univ. of Connecticut), Program Chair
4:10 - 5:00	Thursday Keynote: Technology Characterization for Successful Products Dennis Ciplickas (PDF Solutions)

5:10 PM - 6:50 PM	Session 1 - Defect-based Testing and Test Quality Chair - Xiaoqing Wen (Kyushu Institute of Technology)
5:10 - 5:40	Generating High Quality Test Sets - how do we get there? (Invited Talk) Nilanjan Mukherjee (Mentor Graphics)
5:40 - 6:10	Linking Design and Test for Yield Learning through STDF (Invited Talk) Ajay Koche (Verigy)
6:10 - 6:30	The Economics of Defect-Based Testing Chris Allsup (Synopsys)
6:30 - 6:50	VDD-Ramp Test for Analog Circuits and Optimum Sampling Frequency Selection M. Arabackyj, J. Ortner and W. Schirmer (Universität Erlangen-Nürnberg)

7:00 PM - 9:00 PM WELCOME RECEPTION

October 31, 2008 (Friday)

8:00 AM - 9:00 AM	Tutorial: Green Eggs and Ham - An Outlier Elimination Tutorial. What should be thrown away? What should we keep? Jeffery L. Roehr (MediaTek)

9:00 AM - 10:20 AM	Session 2 - POWER-AWARE TEST Chair - Qiang Xu (Chinese Univ. Of Hong Kong)
9:00 - 9:20	GA-Based X-Filling for Reducing Launch Switching Activity in At-Speed Scan Testing Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, and Seiji Kajihara (Kyushu Institute of Technology)
9:20 - 9:40	On a Dynamic Monitoring Approach for Power Noise Claude Thibeault (Ecole de technologie superieure)
9:40 - 10:00	An Efficient Algorithm for Achieving Constant Test Power Zhongwei Jiang and Hank Walker (Texas A&M University)
10:00 - 10:20	Explore the Limits to Reduce Test Power Shaochong Lei (Xian JiaoTong Univ.), Z. Jiang, and D. M. H. Walker (Texas A&M Univ.)

10:20 AM - 10:40 AM COFFEE BREAK

10:40 AM - 12:00 PM	Session 3 - SIGNAL AND POWER INTEGRITY Chair - Suriyaprakash Natarajan (Intel)
10:40 - 11:00	Identification of IR-drop Hot-spots in Defective Power Distribution Network Using TDF ATPG Junxia Ma, Jeremy Lee, Mohammad Tehranipoor (Univ. Of Connecticut), Xiaoqing Wen (KIT Univ.), Al Crouch (Asset-Intertech)
11:00 - 11:30	Timing closure: Requirements for Variation Aware Design (Invited Talk) Ayhan Mutlu (Extreme DA)
11:30 - 12:00	Plugging Some Limitations of Structural Testing (Invited Talk) Sreejit Chakrabarty (LSI Logic)

12:00 PM - 1:00 PM LUNCH

1:00 PM - 2:20 PM	Session 4 - YIELD AND DATA ANALYSIS Chair - TBD
1:00 - 1:30	Collecting Realistic Data for Parametric Yield (Invited Talk) Amit Majumdar (AMD)
1:30 - 2:00	Title: TBD (Invited Talk) Author: TBD
2:00 - 2:20	A Flexible Scan Architecture to Enable Detection of Stuck-at and Small Delay Defects of a Multi-core Microprocessor Design Talal Jaber and David Wu (Intel)

2:20 PM - 2:30 PM SHORT BREAK

2:30 PM - 4:00 PM	Panel Discussion - Challenges in Test Data Collection & Analysis Organizers: Adit Singh (Auburn Univ.) Mohammad Tehranipoor (Univ. of Connecticut)
	Participants: Keith Arnold (Pintail) Bruce Cory (Nvidia) Mike Laisne (Qualcomm) Jay Orbon (Verigy) Al Crouch (Asset-Intertech)

Committees

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Organizing Committee

General Chair
Rob Aitken, ARM

Program Chair
Mohammad Tehranipoor, Univ. of Connecticut

Vice Program Chair
Al Crouch, Asset-Intertech

Finance Chair
Sankaran M. Menon, Intel

Publicity Chair
Arani Sinha, AMD

Program Committee

Tom Bartenstein, Cadence
Ken Butler, TI
Krish Chakrabarty, Duke Univ.
Sreejit Chakravarty, LSI Logic
John Carulli, TI
Robert Daasch, Portland State Univ.
Jennifer Dworak, Brown University
Patrick Girard, LIRRM
Rohit Kapur, Synopsys
Ajay Koche, Verigy
Mike Laisne, Qualcomm
Nilanjan Mukherjee, Mentor Graphics
Teresa McLaurin, ARM
Martin Margala, U-Mass
Amit Nahar, TI

Steering Committee

Sankaran Menon, Intel
Adit Singh, Auburn Univ.
Hank Walker, Texas A&M
Hans Manhaeve, Q-Start Test
Jim Plusquellic, U. New Mexico

For more information, visit us on the web at: http://d3t.tttc-events.org/

The Defect and Data-Driven Testing (D3T 2008) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC) and the IEEE Computer Society Design Automation Technical Committee.